OpenAI and Synopsys unveil GPT-Synopsys, a model that drives Synopsys EDA tools

The joint service bundles compute, model, and licenses and claims customer design data is protected. Would Nvidia really send its chip designs to OpenAI? I doubt it.

A fox starting a chicken coop business. That is what this looks like.

Give us more open source EDA tools instead of another hyped EDA vendor partnership.

The goal is obviously the opposite. Tool calls move to the other side, you download the finished result at a price or arrange manufacturing, and you never learn what is in the black box.

We just buried an almost finished ASIC. A deviation needed a mask change, and with AI chip demand the manufacturer quoted so much we walked away. AI makes design cheaper and manufacturing so expensive we cannot afford it anymore.

AI did not make manufacturing expensive. Fabs choosing not to scale with demand did, and that should get fixed within a decade.

Local manufacturing is the next open problem in hardware. If a pizza can be baked locally, why not chips?

So agents do all the engineering work and engineers delegate and review. Lol, no. What engineers actually do next is get laid off.

Most of them, and the cutoff bar keeps rising.

Chip design is expensive from engineering and manufacturing both. If LLMs and manufacturing innovation cut costs, more chips get designed, which offsets some of the job losses.

Timing matters: 2 years versus 10 years is a different world. I think SWEs are cooked in 5, but we will be busy fixing the bugs AI finds in the meantime.

Prompt injection in hardware. What could possibly go wrong.

Proprietary locked down EDA means no data to train models, so models suck at it, so the lab reaches out to RL on the vendor's tools, and then users pay for both the EDA and the model.

Something like JLCPCB but for chips would be revolutionary, but masks cost far more than PCBs and direct e-beam prototyping does not scale. Tiny Tapeout is the closest thing and it is still slow and pricey.

I wrote a lot of Tcl glue for PrimeTime and ICC. The hard part was never the constraints, it was knowing which timing violation to believe.

Are formal methods more normal in chip design than in software? For an Arm microcontroller, do engineers formally prove every component? If so, why does silicon errata exist?

It is called design verification, and formal proofs mostly live at the EDA tool level. Errata persist because writing the right assertions is hard and formal verification is exponential, so some designs just will not run on your server.

Logical equivalence checking is the most common formal method, catching synthesis bugs. Property checking with SystemVerilog assertions is what I use, and it is easy to write assertions that pass while proving nothing.

SNPS ticked up on this, but it has not recovered years of losses. EDA never got the hype that AI labs and chip designers did.

After the Kimi K3 buzz about an open model designing its own chip, this was only a matter of time. I can still picture the meeting where the C suite decided to partner externally instead of building in house.